1. Field of Invention
The invention relates to semiconductor-based electronic devices, and, more particularly, to the structure and fabrication of semiconductor-based substrates and electronic devices that include strained semiconductor layers.
2. Discussion of Related Art
Some advanced semiconductor-based devices include a semiconductor layer that is strained by application of a stress to provide improved performance of the devices. For example, metal-oxide-semiconductor (MOS) transistors having a channel formed in strained silicon or strained Si1-yGey formed on unstrained, or relaxed, Si1-xGex, can exhibit improved carrier mobility in comparison to traditional p-type MOS (PMOS) and n-type MOS (NMOS) transistors. Strained-layer MOS transistors can be formed on “virtual substrates,” which include a strained layer to provide compatibility with traditional silicon-based fabrication equipment and methods that were designed for use with conventional silicon wafers. A virtual substrate, in contrast to a conventional wafer, typically includes a strained silicon layer grown on a relaxed and/or graded Si1-xGex layer in turn grown on a silicon substrate.
To fabricate high-performance devices on these platforms, thin strained layers of semiconductors, such as Si, Ge, or Si1-yGey, can be grown on the relaxed Si1-xGex of a virtual substrate. The resulting biaxial tensile or compressive strain of the grown layers alters their carrier mobilities, enabling the fabrication of high-speed and/or low-power devices.
The relaxed Si1-xGex layer of a virtual substrate can in turn be prepared by, e.g., wafer bonding or direct epitaxy on Si, or by epitaxy on a graded SiGe buffer layer in which the lattice constant of the SiGe material has been gradually increased over the thickness of the buffer layer. The virtual substrate may also incorporate buried insulating layers, in the manner of a silicon-on-insulator (SOI) wafer. Deposition of a relaxed graded SiGe buffer layer enables engineering of the in-plane lattice constant of a relaxed Si1-xGex virtual substrate layer (and therefore the amount of strain the relaxed layer will induce in a strained silicon layer or other overlying layer,) while also reducing the introduction of threading dislocations, which can be deleterious to device layers fabricated on the top-most region of the wafer. The lattice constant of Si1-xGex is larger than that of Si, and is a function of the amount of Ge in the Si1-xGex alloy.
Unfortunately, Si1-xGex-based substrates can increase the complexity of device fabrication. For example, source and drain contact metallurgy is altered, and interdiffusion between Si1-xGex layers and neighboring layers can occur. As an alternative to a Si1-xGex-based substrate, strained silicon can be provided on an oxide layer of a substrate. The presence of the oxide layer, however, forces process modifications. Further, oxide layers and Si1-xGex layers have reduced thermal conductivity in comparison to conventional silicon wafers. A reduced thermal conductivity can cause an increase in the difficulty of removing heat at a sufficient rate from devices formed on a substrate.